The Really Good Pedal Co.
Spin FV-1
Spin FV-1
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The Spin Semiconductor FV-1 is a complete reverb solution in a single IC. With integrated stereo ADC and DACs, the FV-1 can be treated like any other analog component in your product's signal path.
The FV-1 can access a total of 16 programs, 8 are built into the internal ROM and the designer may elect to connect a serial EEPROM with 8 additional programs. By using an external EEPROM, the designer can distinguish his product from others by creating a custom program set without the need for a microprocessor in the system.
With 3 potentiometer inputs, programs may have real time variable parameters such as decay time in a reverb, rate and depth in a chorus or frequency in a filter. These inputs are available as coefficients to your program and may be used independently of each other.
The rich instruction set allows users to program effects of all kinds. With instructions like LOG and EXP, users can easily program audio expansion and compression routines. Integrated digital LFOs and ramp generators allow for programming chorus, flange and pitch shift.
Features
- Integrated stereo ADC and DAC
- 8 internal demonstration programs + 8 external programs
- Easy customization with external EEPROM
- 3 potentiometer inputs for real-time parameter adjustment
- 3.3V operation
- 6 MIPS operation at Fs=48KHz
- 128 instructions/sample clock
- 32K words of delay RAM
- Internal PLL for Fs input clock
- Integrated Power-On-Reset circuit
- LOG and EXP instructions for dynamics
- Green assembly/RoHS compliant
Applications
- Guitar Amps
- Mixers
- Effects Equipment
- Karaoke
- Consumer electronics
- Car audio
- Active loudspeaker crossover and flattening
- Industrial processes
Programs
- Chorus-reverb
- Flange-reverb
- Tremolo-reverb
- Pitch shift
- Pitch-echo
- Reverb 1
- Reverb 2
The DSP core of the FV-1 provides many advanced features and instructions that allow you to create advanced programs to make your product stand out. The DSP core consists of the MAC/ALU where all math and logic instructions take place, the LOG and EXP blocks that perform the log and exponential functions, a 32-register bank separate from the delay RAM and LFO and ramp generators that can offset memory addressing.
